1. Field of the Invention
The invention relates to a circuit for synchronizing a digital arrangement with an external clock pulse signal, the digital arrangement comprising a calculating unit receiving during each one of its cycles to be synchronized with the exteral clock pulse signal both an external information to be entered into a buffer store and, thereafter, a sequence of coefficients originating in a predetermined order from a circulating store formed by a number of shift registers equal to the number of coefficients, these shifts registers being shifted by pulses derived from a main clock pulse generator.
2. Description of the Prior Art
The problem of synchronizing a digital arrangement of this type with an external clock pulse signal is, for example, encountered in a digital receiver for a data transmission system. In this case the relevant digital arrangement may be an auto-adaptive passband or baseband equalizer which, as known, processes the received data by means of the automatically adjusted coefficients to compensate for the effects of the distortions of the transmission channel.
In this example, the receiver includes a clock recovery circuit to derive from the received data signal an external clock pulse signal in synchronism with the clock frequency of the data. The received data are coded in the rhythm of the external clock and transferred to a buffer store. During data transmission the equalizer operates correctly if, after each characteristic transition of the external clock pulse signal, an operating cycle of constant duration for the calculating unit is started, each cycle comprising a first time interval for entering an external information into the buffer store and a second time interval for directing the sequence of the coefficients stored in the circulating store to the calculating unit, which coefficients must appear in a predetermined order, that is to say beginning with a first predetermined coefficient and ending with a last predetermined coefficient.
This synchronization of the operating cycles of the calculating unit poses a problem which has not been solved so far in a satisfactory manner if the use of dynamic shift registers in the circulating store is desirable. It is known that these registers must be continuously supplied with shift pulses as otherwise the stored information may get lost.
The known synchronizing circuits utilize a circulating store implemented in a conventional manner with registers arranged in cascade to form a loop so that, if the registers are continuously supplied with shift pulses, the sequence of coefficients appears continuously at the output of the circulating store. To have the sequence of coefficients appear in the required predetermined order in each operating cycle of the calculating unit a shorter or longer interruption in the shift pulses cannot be avoided. In a known circuit, for example, the shift pulses are interrupted at the end of each cycle, that is to say when the last coefficient of the sequence of coefficients has appeared, and they are restored at the beginning of the next cycle to have the first coefficient of the sequence appear at once. Therefore an interruption of the shift pulses is produced in such a circuit between each cycle during the data transmission and in order to acquire synchronization for a new transmission, the duration of the interruption may reach a value in the order of magnitude of one clock period of the data.